Silicon nanowires with sub 10 nm lateral dimensions: From atomic force microscope lithography based fabrication to electrical measurements

The ability of the atomic force microscope ~AFM! to realize lithography patterns on silicon surfaces is widely known and leads to the formation of silicon nanostructures after an etching step. In this article, we aim at improving the fabrication process to yield silicon nanowires with minimum lateral dimensions for the realization of Coulomb blockade based devices. First, we focus on the AFM lithography step: using pulsed voltages for the anodic oxidation of the silicon surface instead of the commonly employed continuous polarization, we obtain an improvement of both AFM lithography resolution and tip reliability. Second, after the wet etching step, we present a technique of oxidation/ deoxidation cycles, which allows a controlled thinning of the silicon wires. Combining these two techniques, we obtain silicon nanowires the widths of which are lower than 10 nm. Finally, as the wires are made on a silicon on insulator substrate, it opens the way to electrical characterization and we present some realizations and results. © 2002 American Vacuum Society. @DOI: 10.1116/1.1470519#